About the Position:
VLSI design/develpment for large, complex high-speed ASIC's and FPGAs for Juniper's next generation of networking products.
Develop the architecture and micro-architecture of high-speed networking ASICs and FPGAs. Implement the design in Verilog or System Verilog. Synthesize the design using Industry standard ASIC/FPGA tools. Work with the Physical Design team to optimize the physical design layout and fix timing issues. Work with the Verification team to verify your block. Show leadership and provide guidance to junior engineers.
Requires a BS/MS EE or equivalent plus 10 years of industry experience.
Strong Verilog, or SystemVerilog skills.
Strong SystemC or C/C+
• and Perl/shell scripts skills.
Knowledge of Synopsys Design Compiler is highly desirable.
Knowledge of FPGA design tools is highly desirable.
Must have good leadership/communication skills.
Networking experience is highly desirable, but not required.
Juniper Networks provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation and training.