Senior Wireless Design Verification Engineer

Apple Inc. Santa Clara, CA

Job Summary

Wireless Design Verification Engineer will be responsible for pre-silicon RTL verification of communication subsystem including MAC, PHY, and interfaces. With deep understanding of communication systems and protocols, the individual will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.

Key Qualifications

7+ years Wireless/Wired communication block/system verification experienceAdvanced knowledge of SystemVerilog and DV methodology.Solid verification skills in problem solving, constrained random testing, and debugging.Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee a plus.Experience with MAC or PHY Verification a plus.Experience with SOC subsystem verification a plus.Experience with SystemVerilog Assertion (SVA) a plus.Should be a team player with excellent communication skills and the desire to take on diverse challenges.

Description

* Build block / subsystem / chip level testbench using best in class DV methodology.• Create verification plan from specification and review with designers and systems engineers.• Architect testbench with maximum reusability in mind, and create UVM libraries.• Generate directed and constrained random tests.• Debug failures, manage bug tracking, and close coverage.• Create/analyze block / subsystem level coverage model, and add test cases to increase coverage.• Attend verification reviews and set standard for coding quality.• Work closely with DV methodology architects to improve verification flow.

Education

Typically requires MSEE with over 7 years of verification experience.