Hardware Design Engineer: GPU Cache 67042

Advanced Micro Devices, Inc. Santa Clara, CA
What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

AMD's GPU design team is seeking an experienced ASIC Design Engineer to design the cache system for the GPU. This position is for a design engineer in AMD's graphics group working on next generation graphics architectures. Our focus is on design of the high performance shader complex that supports advanced graphics rendering and highly parallelized scientific computing.

We are looking for candidates with:

Strong technical skills

Good communication skills

Ability to develop complex system designs

Experience in the following areas is valuable:

High performance processor designs, particularly highly parallel compute systems; GPUs, DSPs or other novel systems

Cache systems, particularly multiple level caches and multiprocessor cache schemes

High performance graphics hardware architecture

The successful candidate will:

Be responsible for a block's hardware design.

Collaborate with architects to translate the block's functional requirements into the block micro architectural specification.

Be responsible for implementing the block Register Transfer Level (RTL) in hardware description language.

Be responsible for synthesizing the RTL to generate the logic gate result.

Assist physical design teams in timing closure.

Collaborate with the block verification team on the block test plan.

Add functional coverage visibility to the design and provide coverage analysis.

Debug block test failures.

Support post-silicon debug efforts.

Qualifications:

Master's degree and 3 or more years' experience; or Bachelor's degree and 5 or more years' experience. Degree in Electrical or Computer Engineering preferred.

Knowledge of computer architecture, including memory sub-systems, cache hierarchies, and pipelined design.

Experience with hardware description languages like Verilog or VHDL.

Experience with synthesis tools (e.g. Synopsys Design Compiler, Cadence RTL compiler, etc.).

Experience with Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Encounter, etc.).

Experience with RTL Linting tools (e.g., Cadence Conformal Lint, Synopsys LEDA, Atrenta Spyglass, etc.).

Experience with RTL logical equivalency checking tools (e.g. Synopsys Formality, Cadence Conformal LEC, etc.).

Requisition Number: 67042

Country: United States State: California City: Santa Clara

Job Function: Design

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers. We consider candidates regardless of age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status. Please click here for more information.

Nearest Major Market: San Jose

Nearest Secondary Market: Palo Alto

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